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Kharchenko V. Fault-tolerant SoPC-based approaches with multi-version IIP [Електронний ресурс] / V. Kharchenko, J. Prokhorova, S. Ostroumov, V. Kulanov // Радіоелектронні і комп’ютерні системи. - 2007. - № 8. - С. 71–77. - Режим доступу: http://nbuv.gov.ua/UJRN/recs_2007_8_15 In this paper different approaches of Infrastructure Intellectual Property (IIP) implementation for System-on-Programmable-Chip (SoPC) are discussed. Several diversity-oriented SoPC approaches and different techniques of checking and reconfiguration for fault-tolerant SoPC FPGA-based projects are proposed. It is described features of two-version IIP development for application, in particular Ice Protection System (IPS).
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Ostroumov S. В. Event-B patterns for developing FPGA-based hardware [Електронний ресурс] / S. В. Ostroumov, L. V. Laibinis, E. A. Troubitsyna // Радіоелектронні і комп’ютерні системи. - 2010. - № 6. - С. 154–160. - Режим доступу: http://nbuv.gov.ua/UJRN/recs_2010_6_28 The paper describes the first step of methodology for designing dependable hardware which is based on field programmable gate array technology. This step means the development of patterns using Event-B language useful thanks to mathematical proofs of a model. The report shows and describes the patterns developed according to synchronism technique because a great number of systems are synchronous. The patterns describe different component interconnections which are often used in hardware design. These patterns are the necessary condition to convert correctly developed model into hardware description language (e.g. VHDL).
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